Power semiconductors such as IGBT's are used for switching electrical current on and off in different devices, such as converters, inverters and frequency converters. If the specified current is very high or scalability and modularity are called for, several such devices can be controlled in parallel.
In these cases, problems can arise with current balancing between different parallel branches. If, because of differences in individual power semiconductors, one semiconductor turns on earlier than the other, it is subjected to more stress than the other.
One method to prevent this is to provide a separate output filter, e.g., an inductor or a filter, for each power semiconductor and combine the currents after the filter. The problems in this approach are cost, complexity and possible resonance issues.
Another approach is to control all variables of the different branches to be as equal as possible. In practice this would mean measuring and choosing similar power semiconductors and having similar regulated gate control voltages for each controlled component. The choosing of matching semiconductors adds costs and produces difficulties if one of the semiconductors should be replaced later.
Another approach is to measure separately the current of each branch having very good dynamic performance. Turn-on and turn-off times can then be fine-tuned for each branch by changing the timing of the switching so that each branch switches simultaneously.
One solution for distributing the timing information is to deliver the time of an actual current change from each power semiconductor unit (PSU) to the central control unit (CCU). Each power semiconductor unit thus measures the actual time instant of the state change and sends this information to the central control unit. The central control unit controls the power semiconductors by sending control information to the power semiconductor units. In a known structure the CCU fine-adjusts the timing information separately for each of the power semiconductors for both turn-on and turn-off.
In another solution the power semiconductor units communicate to each other their delays for finding the slowest unit. Once the slowest unit is found, each PSU increases its delay such that simultaneous switching is achieved. However, the communication between the different PSU's adds to the complexity of the system.
Various network topologies exist for distributing the timing information. When a star topology with the CCU as central node is used, each PSU receives the timing information at different times due to variations in the communication delays between different units. As an alternative to the star topology, a traditional chain or ring topology could be formed. This is to say that the route for timing information is CCU->PSU_1->PSU_2-> . . . ->PSU_n, n being the number of power semiconductor units. In a chain topology the delay for different PSU's is always different and increases towards the end of the chain or ring.
The known systems of distributing timing information use somewhat complex communication even between the power semiconductor units and call for a calculation that is dependent on the delays of other units.